1. Field of the Invention
The present invention relates generally to improvements in digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) utilizing oversampled operation internally. More particularly, the present invention relates to significantly simplified circuitry for DACs and ADCs using dynamic element matching techniques without a reduction in signal quality.
2. State of the Art
Modern semiconductor technologies require ever smaller feature sizes and circuits. While digital processing of signals makes the achievement of higher performance and smaller circuits possible, the trend to smaller circuits makes the design of low noise analog systems more difficult. Effective conversion circuitry between analog and digital systems therefore is becoming more important as semiconductor technologies shrink. Digital-to-analog converters (xe2x80x9cDACxe2x80x9ds) and analog-to-digital converters (xe2x80x9cADCxe2x80x9ds) are widely used in electronic devices to convert signals between analog and digital circuitry.
Mismatches in DAC and ADC elements in audio and other systems can create harmonic distortion (i.e., linearity errors) in the signals carried therein. These errors are reduced or eliminated by employing conventional dynamic element matching (DEM) algorithms which convert linearity errors into a noise signal uncorrelated to the input signal. Noise-shaped DEM techniques are useful in oversampled converters, allowing linearity errors to be translated into noise that is pushed toward out-of-band regions of the frequency spectrum.
The frequency spectrum of a signal is a frequency-domain interpretation of a signal and refers to the frequencies which are detected by or of interest to the person or circuit receiving the signal. This is also called the xe2x80x9csignal band.xe2x80x9d In the case of audio DACs, ultimately the only frequencies of concern are those in the audio signal band which can be heard by people, typically assumed to be about 20 Hz to 20 kHz. However, audio DAC circuitry is capable of running at much higher speeds and has some amount of signal energy from DC to far into the MHZ range. An oversampling audio DAC, which conventionally uses a delta-sigma modulator, makes use of the regions in the frequency spectrum outside of the audio signal band, i.e., below 20 Hz and above 20 kHz, in order to provide a low noise, high quality signal in the audio signal band (20 Hz to 20 kHz). However, delta-sigma modulators may generate additional quantization noise outside the signal band. Dynamic element matching (DEM) techniques also take advantage of this to provide good quality conversion in the signal band region even in the presence of a mismatch, while causing more noise in out-of-band regions.
Existing DEM techniques use multiple unit DAC elements and require an exponential increase in circuit complexity as the number of bits in the DAC increases. This is further explained with reference to FIGS. 1A, 1B and 2. A 4-bit DAC 2 having a prior art decoder/processor block 4 is shown in FIG. 1A. FIG. 1B shows an implementation of DAC 2 of FIG. 1A according to the present invention. The decoder/processor circuitry 4 is used to convert the 4-bit input B0,1,2,3 into the 15 control bits C0,1,2 . . . 14 needed to control the individual DAC unit weighting elements 6. FIG. 2 shows one possible implementation of the prior art digital-to-analog converter of FIG. 1A including a detailed implementation of decoder/processor 4 and a back end analog DAC circuit 18 which can be the same as the circuit 2 shown in FIG. 1B. Note that the analog output 19 in FIG. 2 may be a differential analog output signal, which in the implementation shown in FIG. 1B actually is provided using two conductors 19A, 19B, even though the differential analog output signal is shown in FIG. 2 as only a single line 19.
The 4-bit DAC 2 includes 15 DAC unit weighting elements 6-0,1,2 . . . 14, each receiving a corresponding control bit C0,1,2 . . . 14, respectively, that determines if its (+) output is set positive or negative. The (xe2x88x92) output of each of DAC unit weighting elements 6-0,1,2 . . . 14 is opposite to its (+) output. For the DAC 2 shown in FIG. 1B , the weight of each of the (xe2x88x92) outputs 7-0,1,2 . . . 14 is xc2xd, and the weight of each of the (+) outputs 9-0,1,2 . . . 14 also is xc2xd. If the input control bit C for an individual DAC unit element is equal to a xe2x80x9c1xe2x80x9d, its (+) output signal is equal to xc2xd and its (xe2x88x92) output signal is equal to xe2x88x92xc2xd. If the input control bit C for an individual DAC unit element is equal to a xe2x80x9c0xe2x80x9d, its (+) output signal is equal to xe2x88x92xc2xd and its (xe2x88x92) signal is equal to xc2xd. By summing the (+) outputs together by means of summer 11 and summing the (xe2x88x92outputs together by means of summer 13, the outputs Out31  and Out+ are produced on output conductors 19A and 19B, respectively, and each has a value which varies from xe2x88x927.5 to +7.5. Note that for the DAC to produce a differential output of value zero for a particular code, (i.e., Out31  and Out+ are equal), the circuitry will need to be modified, such as by subtracting xc2xd from Out+ and adding xc2xd to Outxe2x88x92 at all times. That is, if xc2xd is subtracted from Out+ and added to Outxe2x88x92 at all times, then a zero level differential output is obtained. Note that the new range of values of Out+ is from xe2x88x927 to +8. The differential output of the DAC, defined as the difference Out+xe2x88x92Outxe2x88x92, now may range from xe2x88x9216 to +14. However, for the purposes of the remaining description herein, this modification to obtain a zero level differential output is not assumed.
Referring to FIG. 2, a digital filter modulator, referred to herein as a xe2x80x9cMODxe2x80x9d, typically including a digital delta sigma modulator, multiple integrators, summers and gain paths, is used as part of the DEM processing portion of the decoder/processing block 4 in the prior art to generate a multi-bit output. Each digital filter modulator 8 has a xe2x80x9cDxe2x80x9d input which receives a digital input signal. Each digital filter modulator 8 also has a C input or control input, and produces a sum on an output conductors 17. The MOD blocks are just the front ends of digital delta sigma modulators (DDSMs) with their D inputs being where the digital input signal is applied, and their C inputs being where the fed-back quantized signal is applied. Typically, there are internal integrators, sum/difference circuits, and gain paths.
FIG. 2 illustrates a block diagram of a processing section used in prior art DACs with dynamic element matching. In FIG. 2, each MOD filter block 8-0,1,2 . . . 13,14 is preceded by a corresponding scaling block 10-0,1,2 . . . 13,14, respectively, which scales the corresponding input signal C0,1,2 . . . 14 by a factor xcex1. In the example shown, if the input signal C for a particular digital filter modulator MOD 8 is xe2x80x9c0xe2x80x9d, the value of its output 17 is xe2x88x928, and if the input signal C is 1, the value of the digital filter modulator output 17 is +7. This scaling is determined by the range of values possible from the B0,1,2,3 inputs. In this case, the B0,1,2,3 inputs are interpreted by the MOD blocks as signed digital numbers with a range from xe2x88x928 to +7. A sort/decision circuit 12 receives the 4-bit input signal B0,1,2,3 and interprets it differently, by first subtracting the minimum signed digital number this input could represent (which in this case is xe2x88x928) from the actual signed digital number. This results in a new number which is only non-negative and is referred to as the code X. The sort/decision circuit 12 then sets X of the C input bits equal to xe2x80x9c1xe2x80x9d, and the rest equal to xe2x80x9c0xe2x80x9d . The sort/decision circuit 12 also sorts the sum inputs 17 from highest value to the lowest value. The sum outputs on conductors 17-0,1 . . . 14 are multi-bit digital values which have not yet been quantized. The sort/decision circuit 12 selects the X sum buses 17 with the largest values, and the bits corresponding to those stages will be set to xe2x80x9c1xe2x80x9ds. The bits corresponding to the rest of the sum outputs 17 are set to xe2x80x9c0xe2x80x9ds. The digital output C0,1,2 . . . 14 of the sort/decision circuit 12 on bus 23 is then input to an analog back-end circuit 18, such as the DAC 2 shown in FIGS. 1A and 1B, to generate the analog output signal on conductor(s) 19. The digital output C0,1 . . . 14 also is fed back to provide control signals to the inputs of the MOD blocks 8-0,1 . . . 14 as explained below.
This system implements a method of producing a xe2x80x9c4-bitxe2x80x9d analog output (with nominally 16 possible analog output levels) using 15 unit weighting elements 8-0,1 . . . 14 each controlled by single-bit control signals C-0,1 . . . 14. In this system, the number of unit weighting elements 0-0,1 . . . 14 that are turned on or off is always determined by the digital input signals B0-3 (possibly with some pipelined clock delay). The analog output level generated will typically have a monotonic mapping to the digital input signal level B0-3. For example, a digital signal level given by B0-3 value of xe2x88x928 may correspond to an analog output level of xe2x88x927.5. A B0-3 level of xe2x88x927 may correspond to an analog output level of xe2x88x926.5. Continuing similarly, a B0-3 level of +7 may correspond to an analog output level of +7.5. As mentioned earlier, this mapping do not provide a possible analog output level of exactly 0, which may be desired, and so the mapping may be modified to provide this. For this example, the mapping described here is assumed. So if the signal B0-3 indicates that a +xc2xd analog output level on conductor (s) 19 is desired, then 8 of the unit weighting elements 6-0,1 . . . 14 will be turned on and 7 of them will be turned off. Similarly, if the signal B0-3 indicates the +7.5 analog output level is desired, then all 15 of the unit weighting elements 6-0,1 . . . 14 will be turned on.
As is well known, in order to prevent mismatch in the unit weighting elements 6-0,1 . . . 14 from introducing harmonic distortion into the information presented by the input signals B0-3, it can be shown that if the one-bit control signals C0,1 . . . 14 that control each unit element 6-0,1 . . . 14 contain very low or no signal harmonic energy, then even in the presence of mismatches of the unit weighting elements there will be little or no harmonic distortion introduced into the analog output on conductor(s) 19 in FIG. 2.
This property is obtained by using a digital delta sigma modulator (DDSM) to generate each controlled signal C0,1 . . . 14 from the original digital input signal B0-3, assuming that the sampling rate is such that the signal band of interest is sufficiently oversampled. There are two objectives of the DEM technique. The first objective is to ensure that the individual control signals contain little or no signal harmonic content and little or no noise in the signal band. The second objective of the DEM technique is that the proper number of unit weighting elements 6-0,1, . . . 14 are turned on to match the number required by the input signal B0-3 as mentioned above. The first objective is important to achieve, since it helps ensure that a high linearity output is obtained with little or no harmonic distortion. The second objective is not absolutely necessary, but it simplifies the design of the entire oversampling DAC system, since the analog back-end will still provide the same nominal (in the sense that the effects of mismatch make it inexact) analog output as it would have if no DEM technique had been used.
In order to accomplish the need for the proper number of unit weighting elements 6-0,1 . . . 14 to be turned on, and to obtain low or no harmonic distortion in the control signals C0, 1 . . . 14, the structure shown in FIG. 2 is used. That structure includes multiple parallel DDSMs with a merged quantizer block (i.e., sort/decision block 12), and the output of sort/decision block 12 generates the digital outputs C0,1 . . . . 14 on the bus 23 to control the unit weighting elements 6-0,1 . . . 14, and is also fed around the DDSMs to the C inputs of each MOD block in FIG. 2. The digital inputs B0-3 on bus 21 are fed to the D inputs of each of the MOD blocks 8-0,1 . . . 14, each of which is essentially a digital delta sigma modulator as described above, only without the quantizer and feedback path. The sort/decision block 12 then looks at the B0-3 digital input and determine from it exactly how many of the control signals C0,1 . . . 14 can be at a high level and how many must be at a low level. Sort/decision block 12 then looks at the sum outputs of each MOD block 8-0,1 . . . 14 on conductors 17-0,1 . . . 14 and sets those MOD blocks with the highest sum outputs to have their control outputs C0-0, 1 . . . 14 at a high level if possible, and after all high settings have been exhausted, the rest of the parallel paths provide low levels on their corresponding control outputs C0,1 . . . 14. This effectively implements 15 parallel DDSMs with the additional the restriction that the number of control outputs C0, 1 . . . 14 that are at a high level is set by the original digital input signal B0-3, so independent quantizer decisions are not used. Instead, the single merged quantizer block (i.e., sort/decision block 12) is used.
As will be clear to one skilled in the art, an 8-bit DAC using the described prior art approach requires 255 unit weighting elements (2Nxe2x88x921 unit weighting elements for an N-bit DAC) in contrast to the 15 unit weighting elements required for a 4-bit DAC. Implementation of an 8-bit DAC in a way similar to that shown in FIGS. 1A, 1B , and 2, with dynamic element matching, also requires 255 control bits and 255 digital filter modulator circuits. Thus, the complexity of the circuitry for a DAC with dynamic element matching increases exponentially with an increase in resolution or number of bits. It should be noted that there are methods of reducing the complexity of the circuitry somewhat, but ultimately there are still 2Nxe2x88x921 modified digital filter modulator circuits required. Even for an 8-bit DAC, this amount of circuitry would require a significant amount of space and power even if the digital filter modulator circuits were reduced to circuitry as simple as a D-flip flop and some combinational logic.
Thus, there is an unmet need for an efficient method of implementing a scheme similar to dynamic element matching for DACs having a large number of possible output levels, without exponentially increasing the amount of circuitry as the number of possible DAC output levels increases exponentially.
Accordingly, it is an object of the invention to provide a DAC using techniques somewhat similar to dynamic element matching techniques in which circuit complexity increases linearly, rather than exponentially, with an increase in bit capacity.
It is another object of the invention to reduce erroneous signals within the signal band caused by quantization and other processing noise in DAC and ADC circuits.
It is another object of the invention to provide a DEM-like technique that can be used to provide oversampling DAC circuits and ADC circuits that are more stable, more robust, have lower analog circuit noise for a given power dissipation, and have lower noise tones than has been previously achievable.
The present invention provides a method and apparatus for enhancing signal quality in circuits employing noise-shaped dynamic element matching techniques. The present invention accomplishes this in a particularly useful way which enables circuit complexity to increase linearly rather than exponentially. In a particular embodiment of a DAC configured according to the present invention, the DAC includes a plurality of delta-sigma modulators, each receiving an appropriate digital input signal from a processor circuit and generating a control signal for a binary weighted converter element. The sum of the outputs from each of the weighted converter elements is an analog signal representative of the digital input signal. Because the control signals each include erroneous signal components, such as quantization noise, in addition to desired signal components, the output of each of the weighted converter elements is erroneous to some extent. To compensate for the error signals, the control signal of a binary weighted converter element of heavier weight is sampled and a portion of the signal included in the input signal for a modulator feeding a binary weighted converter element of lighter weight. This process is repeated for all but the least significant binary weighted converter element. The result of this process is that when the outputs of the weighted converter elements are summed, the error signals in each of the outputs of the heavier weighted converter elements are cancelled by correction components in each of the lighter weighted converter elements such that only the error resulting through the lightest weighted converter element is included in the analog output.
In an ADC embodiment of the present invention, the DAC circuit described above is included in a feedback circuit of an ADC to reduce quantization noise in the ADC. Additionally, because of the methods and circuits through which this invention is accomplished, rather than requiring an exponential increase in circuit complexity for increased resolution (e.g. 4-bit to 8-bit digital signal), the circuit complexity only increases linearly. This is particularly advantageous for circuits which use dynamic element matching techniques because prior art DEM techniques require substantial additional circuitry and physical die space as the number of DAC output levels is increased, for example, to 128, 256, 512 or above.